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| FAN7317 -- LCD Backlight Inverter Drive IC January 2008 FAN7317 LCD Backlight Inverter Drive IC Features High-Efficiency Single-Stage Power Conversion Wide Input Voltage Range: 6V to 24V Backlight Lamp Ballast and Soft Dimming Minimal Required External Components Precision Voltage Reference Trimmed to 2% ZVS Full-Bridge Topology Soft-Start PWM Control at Fixed Frequency Burst Dimming Function Programmable Striking Frequency Open-Lamp Protection Open-Lamp Regulation Arc Protection Short-Lamp Protection CMP-High Protection High-FB Protection Thermal Shutdown 20-Pin SOIC Description The FAN7317 is a LCD backlight inverter drive IC that controls P-N full-bridge topology by using the new patented phase-shift method. The FAN7317 provides a low-cost solution and reduces external components by integrating full wave rectifiers for open-lamp protection and regulation (patent pending). The operating voltage range of the FAN7317 is wide, so an external regulator isn't necessary to supply the voltage to the IC. The FAN7317 provides various protections, such as open-lamp regulation, open-lamp protection, arc protection, short-Lamp protection, CMP-high protection, and FB-high protection, to increase the system reliability. The FAN7317 provides burst dimming function and analog dimming is possible, in a narrow range, by adding some external components. The FAN7317 is available in a 20-SOIC package. Applications LCD TV LCD Monitor Ordering Information Part Number FAN7317M FAN7317MX Package 20-SOIC 20-SOIC Operating Temperature -25 to +85C -25 to +85C Packing Method RAIL TAPE & REEL All packages are lead free per JEDEC: J-STD-020B standard. Protected under U.S. patent nos. 5,652,479 and 7,158,390. (c) 2007 Fairchild Semiconductor Corporation FAN7317 * 1.0.2 www.fairchildsemi.com FAN7317 -- LCD Backlight Inverter Drive IC Block Diagram Short Lamp Protection Min. 0.3V OLR1 + Arc Protection Disable @ striking 1ms delay (operation @ burst dimming on) OUTA TSD 150oC Protection Disable @ striking OLR output 32 count @ normal Reset by BCT edge detect Output Driver 7V 0.2A/0.3A dead time 200ns + OLR2 Min. & Max. Detector /Full Wave Recifier Max. 2V 3V Over-Voltage Protection OUTB + + 2V OLR3 OLR4 0A 1.6s delay @ striking 10ms delay @ normal OUTC OUTD + 1.8V 1A Error. Amp. source current change - Gm Amp. Open Lamp Regulation 2.2V max. 2V min. 0.5V + Oscillator Control Logic Gm = 350, Max. current 85A On @ striking CT CMP + Error. Amp. source 0A sink current @ striking current change Error Amp. 1.35V + Hys. 0.45V GND UVLO 5.5V + 52A burst sink current on 3V High CMP Protection disable @ striking Linear region 0~4V + - VIN 1.35V High_CMP High FB Protection disable @ striking OLP max. 3.5V + - High_FB Striking off Voltage Reference & Internal Bias 5V, max. 3mA OLP1 OLP2 OLP min. 1V/0.5V Striking/normal + 150s Delay 52A burst sink current on OLP4 Figure 1. Internal Block Diagram (c) 2007 Fairchild Semiconductor Corporation FAN7317 * 1.0.2 2 - OLP3 Min. & Max. Detector /Full Wave Rectifier 4 Output Pulses Counter OLP max. 2V min. 0.5V + + ENA 200k REF BCT BDIM www.fairchildsemi.com FAN7317 -- LCD Backlight Inverter Drive IC Pin Configuration Figure 2. Package Diagram F (c) 2007 Fairchild Semiconductor Corporation FAN7317 * 1.0.2 www.fairchildsemi.com 3 FAN7317 -- LCD Backlight Inverter Drive IC Pin Definitions Pin # 1 2 3 Name REF BDIM BCT Description This pin is 5V reference output. Typically, resistors are connected to this pin from CT pin and BCT pin. This pin is the input for burst dimming. The voltage range of 0.5 to 2V at this pin controls burst mode duty cycle from 0% to 100%. This pin is for programming the frequency of the burst dimming. Typically, a capacitor is connected to this pin from ground and a resistor is connected to this pin from the REF pin. This pin is for open-lamp protection and feedback control of lamp currents. It has the same functions as other OLP pins and is connected to the full-wave rectifier internally. In striking mode, if the minimum of rectified OLP inputs is less than 1V for 1.6s; or in normal mode, if the minimum of rectified OLP inputs is less than 0.5V for 10ms; the IC shuts down to protect the system in open lamp condition. The maximum of rectified OLP inputs is inputted to the negative of the error amplifier for feedback control of lamp current. This pin is for open-lamp regulation. It has the same functions as other OLR pins and is connected to the full-wave rectifier internally. When the maximum of rectified OLR inputs is between 1.8V and 2V, the error amplifier output current is limited to 1A; and when the maximum of rectified OLR inputs reaches 2V, the error amplifier output current is 0A and its output voltage maintains constant. The maximum of rectified OLR inputs is inputted to the negative of another error amplifier for feedback control of lamp voltage. When the maximum of rectified OLR inputs is more than 2.2V, another error amplifier for OLR is operating and lamp voltage is regulated. This pin is for open-lamp protection and feedback control of lamp currents. Its functions are the same as the OLP1 pin. This pin is for open-lamp regulation. Its functions are the same as the OLR1 pin. This pin is the ground. This pin is NMOS gate-drive output. This pin is PMOS gate-drive output. This pin is PMOS gate-drive output. This pin is NMOS gate-drive output. This pin is the supply voltage of the IC. This pin is for open-lamp regulation. Its functions are the same as the OLR1 pin. This pin is for open-lamp protection and feedback control of lamp currents. Its functions are the same as the OLP1 pin. This pin is for open-lamp regulation. Its functions are the same as the OLR1 pin. This pin is for open-lamp protection and feedback control of lamp currents. Its functions are the same as the OLP1 pin. This pin is for turning on/off the IC. Error amplifier output. Typically, a compensation capacitor is connected to this pin from the ground. This pin is for programming the switching frequency. Typically, a capacitor is connected to this pin from ground and a resistor is connected to this pin from the REF pin. 4 OLP1 5 OLR1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 OLP2 OLR2 GND OUTB OUTA OUTC OUTD VIN OLR3 OLP3 OLR4 OLP4 ENA CMP CT (c) 2007 Fairchild Semiconductor Corporation FAN7317 * 1.0.2 www.fairchildsemi.com 4 FAN7317 -- LCD Backlight Inverter Drive IC Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VIN TA TJ TSTG JA PD IC Supply Voltage Parameter Operating Temperature Range Operating Junction Temperature Storage Temperature Range Thermal Resistance Junction-Air Power Dissipation (1,2) Min. 6 -25 -65 Max. 24 +85 +150 +150 90 1.4 Unit V C C C C/W W Notes: 1. Thermal resistance test board. Size: 76.2mm x 114.3mm x 1.6mm (1S0P); JEDEC standard: JESD51-2, JESD51-3. 2. Assume no ambient airflow. Pin Breakdown Voltage Pin # 1 2 3 4 5 6 7 8 9 10 Name REF BDIM BCT OLP1 OLR1 OLP2 OLR2 GND OUTB OUTA Value 7 7 7 7 7 7 7 7 7 24 Unit Pin # 11 12 13 14 15 16 17 18 19 20 Name OUTC OUTD VIN OLR3 OLP3 OLR4 OLP4 ENA CMP CT Value 24 7 24 7 7 7 7 7 7 7 Unit V V (c) 2007 Fairchild Semiconductor Corporation FAN7317 * 1.0.2 www.fairchildsemi.com 5 FAN7317 -- LCD Backlight Inverter Drive IC Electrical Characteristics For typical values, TA = 25C, VIN = 15V, and -25C TA 85C, unless otherwise specified. Specifications to -25C ~ 85C are guaranteed by design based on final characterization results. Symbol Parameter Test Conditions Min. Typ. Max. Unit Under-Voltage Lockout Section (UVLO) Vth Vthhys Ist Iop Start Threshold Voltage Start Threshold Voltage Hysteresis Start-up Current Operating Supply Current VIN = 4.5V VIN = 15V, Not switching 4.9 0.20 5.2 0.45 70 2.0 5.5 0.60 100 3.5 V V A mA ON/OFF Section Von Voff Isb RENA On State Input Voltage Off Stage Input Voltage Stand-by Current Pull-down Resistor VIN = 15V, ENA = Low 130 120 200 2 5 0.7 170 270 V V A k Reference Section (Recommend 1F X7R Capacitor) V5 V5line V5load 5V Regulation Voltage 5V Line Regulation 5V Load Regulation 0 I5 3mA 6 VIN 24V I5 = 3mA 4.9 5.0 5.1 50 50 V mV mV Oscillator Section (Main) TA = 25C, CT = 220pF, RT = 100k CT = 220pF, RT = 100k TA = 25C, CT = 220pF, RT = 100k CT = 220pF, RT = 100k Striking Normal Striking 93.9 93 120 119 0.99 740 -15 97.0 97 124 124 1.14 840 -12 2 0.4 100.5 kHz 101 129 kHz 129 1.29 940 -9 mA A A V V fosc Oscillation Frequency fstr Oscillator Frequency in Striking Mode Ictdcs Ictdc Ictcs Vcth Vctl CT Discharge Current CT Charge Current CT High Voltage CT Low Voltage Oscillator Section (Burst) TA = 25C, BCT = 4.7nF, BRT = 1.4M BCT = 4.7nF, BRT = 1.4M 303 302 14 314 314 26 2 0.5 326 Hz 326 38 A V V foscb Burst Oscillation Frequency Ibctdc Vbcth Vbctl BCT Discharge Current BCT High Voltage BCT Low Voltage (c) 2007 Fairchild Semiconductor Corporation FAN7317 * 1.0.2 www.fairchildsemi.com 6 FAN7317 -- LCD Backlight Inverter Drive IC Electrical Characteristics (Continued) For typical values, TA = 25C, VIN = 15V, and -25C TA 85C, unless otherwise specified. Specifications to -25C ~ 85C are guaranteed by design based on final characterization results. Symbol Error Amplifier Section AV Gm lsin lsur Ibsin V135p Iolpi Iolpo Volpr Open-loop Gain (3) Parameter Test Conditions Min. Typ. Max. Unit 37 20 OLP = 2.25V OLP = 0.8V -50 12 38 TA = 25C OLP = 2V OLP = -2V (3) dB 60 -20 32 66 1.421 1.444 1 -10 4 mho A A A V A A V Error Amplifier Trans-conductance Output Sink Current Output Source Current Burst CMP Sink Current 1.35V Regulation Voltage OLP Input Current OLP Output Current OLP Input Voltage Range 40 -35 22 52 1.350 1.350 0 -20 1.275 1.255 -1 -30 -4 Open-Lamp Regulation Section Iolr1 Iolr2 Volr1 Volr2 Volr3 GmOLR Iolrsi Iolri Iolro Volrr Error Amplifier Source Current for Open-Lamp Regulation Open-Lamp Regulation Voltage 1 Open-Lamp Regulation Voltage 2 Open-Lamp Regulation Voltage 3 OLR Error Amplifier Transconductance OLR Error Amplifier Sink Current OLR Input Current OLR Output Current OLR Input Voltage Range (3) Striking, OLR = Volr1+0.05 OLR = 2.1V Striking Striking -2.0 -1.0 0 -0.1 A A 1.65 1.95 2.1 200 1.80 2.05 2.2 350 70 17 -15 1.95 2.15 2.3 500 90 24 -7 4 V V V mho A A A V Normal, OLR = 2.5V OLR = 1.5V OLR = -1.5V 50 10 -25 -4 Note: 3. These parameters, although guaranteed, are not 100% tested in production. (c) 2007 Fairchild Semiconductor Corporation FAN7317 * 1.0.2 www.fairchildsemi.com 7 FAN7317 -- LCD Backlight Inverter Drive IC Electrical Characteristics (Continued) For typical values, TA = 25C, VIN = 15V, and -25C TA 85C, unless otherwise specified. Specifications to -25C ~ 85C are guaranteed by design based on final characterization results. Protection Section Volp0 Volp1 Vcmpr Varcp Vhfbp Vslp Tolps Tolpn Tcmprs Tcmprn Tolr Tslp TSD Open-Lamp Protection Voltage 0 Open-Lamp Protection Voltage 1 CMP-High Protection Voltage Arc Protection Voltage High-FB Protection Voltage (4) (4) Open Lamp in Striking Open Lamp 0.95 0.44 2.95 2.90 3.4 0.24 1.00 0.51 3.05 3.05 3.5 0.32 1.6 10 1.6 10 320 1 150 1.05 0.58 3.15 3.20 3.6 0.40 V V V V V V s ms s ms s ms C Short Lamp Protection Voltage Open-Lamp Protection Delay High-CMP Protection Delay (4) Striking, foscb = 330Hz Normal, fosc = 100kHz Striking, foscb = 330Hz Normal, fosc = 100kHz (4) Open-Lamp Regulation Delay Short Lamp Protection Delay Thermal Shutdown (4) (4) Normal, fosc = 100kHz Normal, fosc = 100kHz (4) Output Section Vpdhv Vphlv Vndhv Vndlv Vpuv Vnuv Ipdsur Ipdsin Indsur Indsin tr tf PMOS Gate High Voltage PMOS Gate Low Voltage NMOS Gate High Voltage NMOS Gate Low Voltage (4) (4) VIN = 15V VIN = 15V VIN = 15V VIN = 15V VIN = 4.5V VIN = 4.5V (4) VIN VIN-6.5 6.5 VIN-7 7.0 0 VIN-0.3 0.3 -200 300 200 -300 70 70 VIN-7.5 7.5 V V V V V V mA mA mA mA ns ns PMOS Gate Voltage with UVLO Activated NMOS Gate Voltage with UVLO Activated PMOS Gate Drive Source Current PMOS Gate Drive Sink Current (4) (4) VIN = 15V VIN = 15V VIN = 15V VIN = 15V VIN = 15V, Cload = 2nF VIN = 15V, Cload = 2nF NMOS Gate Drive Source Current NMOS Gate Drive Sink Current Rising Time (4) (4) (4) Falling Time Maximum / Minimum Overlap Minimum Overlap Between Diagonal (4) Switches Maximum Overlap Between Diagonal (4) Switches Dead Time PDR_A/NDR_B (4) (4) fosc = 100kHz fosc = 100kHz 86 0 90 % % 150 150 200 200 250 250 ns ns PDR_C/NDR_D Note: 4. These Parameters, although guaranteed, are not 100% tested in production. (c) 2007 Fairchild Semiconductor Corporation FAN7317 * 1.0.2 www.fairchildsemi.com 8 FAN7317 -- LCD Backlight Inverter Drive IC Typical Performance Characteristics Figure 3. Start Threshold Voltage vs. Temp. Figure 4. Start Threshold Voltage Hys. vs. Temp. Figure 5. Start-up Current vs. Temp. Figure 6. Operating Current vs. Temp. Figure 7. Standby Current vs. Temp. Figure 8. Pull-down Resistor vs. Temp. (c) 2007 Fairchild Semiconductor Corporation FAN7317 * 1.0.2 www.fairchildsemi.com 9 FAN7317 -- LCD Backlight Inverter Drive IC Typical Performance Characteristics (Continued) Figure 9. 5V Regulation Voltage vs. Temp. Figure 10. Oscillation Frequency vs. Temp. Figure 11. Oscillation Frequency in Striking vs. Temp. Figure 12. CT Discharge Current in Striking vs. Temp. Figure 13. CT Discharge Current vs. Temp. Figure 14. CT Charge Current vs. Temp. (c) 2007 Fairchild Semiconductor Corporation FAN7317 * 1.0.2 www.fairchildsemi.com 10 FAN7317 -- LCD Backlight Inverter Drive IC Typical Performance Characteristics (Continued) Figure 15. CT High Voltage vs. Temp. Figure 16. CT Low Voltage vs. Temp. Figure 17. Burst Dimming Frequency vs. Temp. Figure 18. BCT Discharge Current vs. Temp. Figure 19. BCT High Voltage vs. Temp. Figure 20. BCT Low Voltage vs. Temp. (c) 2007 Fairchild Semiconductor Corporation FAN7317 * 1.0.2 www.fairchildsemi.com 11 FAN7317 -- LCD Backlight Inverter Drive IC Typical Performance Characteristics (Continued) Figure 21. Error Amp. GM vs. Temp. Figure 22. Error Amp. Sink Current vs. Temp. Figure 23. Error Amp. Source Current vs. Temp. Figure 24. Burst CMP Sink Current vs. Temp. Figure 25. 1.35V Regulation Voltage vs. Temp. Figure 26. OLP Input Current vs. Temp. (c) 2007 Fairchild Semiconductor Corporation FAN7317 * 1.0.2 www.fairchildsemi.com 12 FAN7317 -- LCD Backlight Inverter Drive IC Typical Performance Characteristics (Continued) Figure 27. OLP Output Current vs. Temp. Figure 28. Error Amp. Source Current 1 vs. Temp. Figure 29. Error Amp. Source Current 2 vs. Temp. Figure 30. OLR Error Amp. GM vs. Temp. Figure 31. OLR Error Amp. Sink Current vs. Temp. Figure 32. OLR Input Current vs. Temp. (c) 2007 Fairchild Semiconductor Corporation FAN7317 * 1.0.2 www.fairchildsemi.com 13 FAN7317 -- LCD Backlight Inverter Drive IC Typical Performance Characteristics (Continued) Figure 33. OLR Output Current vs. Temp. Figure 34. Open-Lamp Protection Voltage1 vs. Temp. Figure 35. High-CMP Protection Voltage vs. Temp. Figure 36. Arc Protection Voltage vs. Temp. Figure 37. Short Lamp Protection Voltage vs. Temp. Figure 38. PMOS Gate Low Voltage vs. Temp. (c) 2007 Fairchild Semiconductor Corporation FAN7317 * 1.0.2 www.fairchildsemi.com 14 FAN7317 -- LCD Backlight Inverter Drive IC Functional Description UVLO: The under-voltage lockout (UVLO) circuit guarantees the stable operation of the IC's control circuit by stopping and starting it as a function of the VIN value. The UVLO circuit turns on the control circuit when VIN exceeds 5.2V. When VIN is lower than 4.75V, the IC start-up current is less than 100A. Burst Dimming Oscillator: The burst dimming timing capacitor (BCT) is charged by the current flowing from the reference voltage source, which is formed by the burst dimming timing resistor (BRT) and the burst dimming timing capacitor (BCT). The sawtooth waveform charges up to 2V. Once the BCT voltage reaches 2V, the capacitor begins discharging down to 0.5V. Next, the BCT starts charging again and a new burst dimming cycle begins, as shown in Figure 40. The burst dimming frequency is programmed by adjusting the BCT and BRT values. The burst dimming frequency is calculated as: ENA: Applying voltage higher than 2V to the ENA pin enables the IC. Applying voltage lower than 0.7V to the ENA pin disables the IC. f OSCB = Main Oscillator: In normal mode, the external timing capacitor (CT) is charged by the current flowing from the reference voltage source, which is formed by the timing resistor (RT) and the timing capacitor (CT). The sawtooth waveform charges up to 2V. Once CT voltage reaches 2V, the CT begins discharging down to 0.4V. Next, the CT starts charging again and a new switching cycle begins, as shown in Figure 39. The main frequency is programmed by adjusting the RT and CT value. The main frequency is calculated as: 1 [Hz] 0.039 BRT - 4500 BRT BCT ln 0.026 BRT - 4500 (3) To avoid visible flicker, the burst dimming frequency should be greater than 120Hz. f OSC = 1 [Hz] 3.864 RT - 13800 RT CT ln 2.52 RT - 13800 (1) Figure 40. Burst Dimming Oscillator Circuit Analog Dimming: For analog dimming, the lamp intensity is controlled with the external dimming signal (VADIM) and resistors. Figure 41 shows how to implement an analog dimming circuit. The polarity of OLP1 should be reversed with respect to OLP2. Figure 39. Main Oscillator Circuit In striking mode, the external timing capacitor (CT) is charged by the current flowing from the reference voltage source and 12A current source, which increases the frequency. If the product of RT and CT value is constant, the striking frequency is depending on CT and is calculated as: f str = 13.8 + (3I1 - 4.6I 2 )RT - I1 I 2 RT 2 RT CT ln 13.8 + (4.6I1 - 3I 2 )RT - I I RT 2 12 1 [Hz] (2) Q I1 = 12 x10 -6 A, I 2 = 1.128 x 10 -3 A (c) 2007 Fairchild Semiconductor Corporation FAN7317 * 1.0.2 www.fairchildsemi.com 15 FAN7317 -- LCD Backlight Inverter Drive IC T1 R1 R2 R2 R1 T2 RS2 RS2 Fullbridge output Burst Dimming: Lamp intensity is controlled with the BDIM signal over a wide range. When BDIM voltage is lower than BCT voltage, the lamp current is turned on; so, 0V on BDIM commands full brightness. The duty cycle of the PWM pulse determines the lamp brightness. The lamp intensity is inversely proportional to BDIM voltage. As BDIM voltage increases, the lamp intensity decreases. Figure 43 shows the lamp current waveform vs. DIM in negative analog dimming mode. 2V VBDIM BCT 0.5V 0 RS1 CMP 0.5V 0 RS1 iLamp 0 Figure 41. Analog Implementation Circuit In full brightness, the maximum rms value of the lamp current is calculated as: VIN(V) OUTA VIN-7(V) 7V i max = 1.35 rms 2 2 R S1 [A] OUTB (4) OUTC 0 VIN(V) VIN-7(V) 7V The lamp intensity is inversely proportional to VADIM. As VADIM increases, the lamp intensity decreases and the rms value of the lamp current is calculated as: OUTD 0 i rms = i max - rms Q R S2 R1 VADIM [A ] 2 2 R S2 R 2 R + R2 R S1 [] =1 R2 Figure 43. Burst Dimming Waveforms (5) Burst dimming can be implemented not only DC voltage, but also using PWM pulse as the BDIM signal. Figure 44 shows how to implement burst dimming using PWM pulse as BDIM signal. Figure 42 shows the lamp current waveform vs. VADIM in an analog dimming mode. tch b tdch b i max Lamp i min Lamp Figure 42. Analog Dimming Waveforms Figure 44. Burst Dimming Using an External Pulse During striking mode, burst dimming operation is disabled to guarantee continuous striking time. Figure 45 shows burst dimming is disabled during striking mode. (c) 2007 Fairchild Semiconductor Corporation FAN7317 * 1.0.2 www.fairchildsemi.com 16 FAN7317 -- LCD Backlight Inverter Drive IC 2V VBDIM BCT 0.5V 0 CMP 0.5V 0 1V Striking mode OLP 0 -1V VIN(V) OUTA VIN-7(V) 7V Open-Lamp Regulation: When the maximum of the max rectified OLR input voltages ( VOLR ) is more than 2V, the IC enters regulation mode and controls CMP voltage. The IC limits the lamp voltage by decreasing CMP max source current. If VOLR is between 1.8V and 2V, CMP source current decreases from 22A to 1A. Then, if max VOLR reaches 2V, CMP source current decreases to 0A, so CMP voltage remains constant and the lamp voltage also remains constant, as shown in Figure 47. max Finally, if VOLR is more than 2.2V, the error amplifier for OLR is operating and CMP sink current increases, so CMP voltage decreases and the lamp voltage maintains the determined value. max At the same time, while VOLR is more than 2V, the counter starts counting 32 rectified OLR pulses in normal mode, then the IC enters shutdown, as shown in Figure 49. This counter is reset by detecting the positive edge of BCT. This protection is disabled in striking mode to ignite lamps reliably. OUTB 0 VIN(V) OUTC VIN-7(V) 7V OUTD 0 Figure 45. Burst Dimming During Striking Mode Output Drives: FAN7317 uses the new phase-shift method for full-bridge Cold Cathode Fluorescent Lighting (CCFL) drive. As a result, the temperature difference between the left and the right leg is almost zero, because ZVS occurs in both of the legs by turns. The detail timing is shown in Figure 46. Figure 47. Open-Lamp Regulation in Striking Mode CMP 0 2.2V 2V 2V OLR 2.2V OLR OLR 0 -2V -2.2V iCMP 0 Figure 46. MOSFETs Gate Drive Signal Figure 48. Open-Lamp Regulation in Normal Mode Protections: The FAN7317 provides the following latchmode protections: Open-Lamp Regulation (OLR), Arc Protection, Open-Lamp Protection (OLP), Short-Lamp Protection (SLP), CMP-High Protection, and Thermal Shutdown (TSD). The latch is reset when VIN falls to the UVLO voltage or ENA is pulled down to GND. (c) 2007 Fairchild Semiconductor Corporation FAN7317 * 1.0.2 www.fairchildsemi.com 17 FAN7317 -- LCD Backlight Inverter Drive IC 5V CMP 0 CMP 0 1.6s 1V Shut down 2V OLP 0 -1V VIN(V) OLR 0 -2V OUTA 32 pulses counting Shut down VIN-7(V) 7V BCT 0 OUTB 0 VIN(V) Counter reset OUTC VIN-7(V) 7V OUTA OUTB 0 OUTD 0 OUTC OUTD 0 Figure 51. Open-Lamp Protection in Striking Mode 5V Figure 49. Over-Voltage Protection in Normal Mode Arc Protection: If the maximum of the rectified OLR max input voltages ( VOLR ) is higher than 3V, the IC enters shutdown mode without delay, as shown in Figure 50. CMP 0 3V CMP 0 10ms 0.5V 0 -0.5V Shut down OLP VIN(V) OUTA VIN-7(V) 7V OUTB 0 VIN(V) OLR 0 OUTC VIN-7(V) 7V Shut down OUTD 0 OUTA OUTB 0 Figure 52. Open-Lamp Protection in Normal Mode Short-Lamp Protection: If the minimum of the rectified min OLR voltages ( VOLR ) is less than 0.3V in normal mode, the IC is shut down after a delay of 1ms, as shown in Figure 53. This protection is disabled in striking mode to ignite lamps reliably. OUTC OUTD 0 Figure 50. Arc Protection Open-Lamp Protection: If the minimum of the rectified min OLP voltages ( VOLP ) is less than 1V during initial operation, the IC operates in striking mode only for 1.6s, min as shown in Figure 51. After ignition, if VOLP is less than 0.5V in normal mode, the IC is shut down after a delay of 10ms, as shown in Figure 52. Figure 53. Short-Lamp Protection (c) 2007 Fairchild Semiconductor Corporation FAN7317 * 1.0.2 www.fairchildsemi.com 18 FAN7317 -- LCD Backlight Inverter Drive IC CMP-High Protection: If CMP is more than 3V in normal mode, the IC is shut down after a delay of 10ms, as shown in Figure 54. This protection is disabled in striking mode to ignite lamps reliably. Figure 54. CMP-High Protection High-FB Protection: If the minimum of the rectified OLP max voltages( VOLP ) is more than 3.5V, the counter starts counting eight rectified OLP pulses in normal mode, then the IC enters shutdown, as shown in Figure 55. This counter is reset by detecting the positive edge of BCT. This protection is disabled in striking mode to ignite lamps reliably. CMP 0 3.5V OLP 0 -3.5V BCT 0 8 pulses counting Shut down Counter reset OUTA OUTB 0 OUTC OUTD 0 Figure 55. High-FB Protection Thermal Shutdown: The IC provides the function to detect the abnormal over-temperature. If the IC temperature exceeds approximately 150C, the thermal shutdown triggers. (c) 2007 Fairchild Semiconductor Corporation FAN7317 * 1.0.2 www.fairchildsemi.com 19 FAN7317 -- LCD Backlight Inverter Drive IC Typical Application Circuit (LCD Backlight Inverter) Application 22-Inch LCD Monitor Device FAN7317 Input Voltage Range 1310% Number of lamps 4 1. Features High-Efficiency Single-Stage Power Conversion P-N Full-Bridge Topology Reduces Required External Components Enhanced System Reliability through Protection Functions 20 19 18 17 16 15 14 13 12 OUTD OUTB 9 VIN OLP1 BDIM REF BCT Figure 56. Typical Application Circuit 2. Transformer Schematic Diagram Figure 57. Transformer Schematic Diagram 3. Core & Bobbin Core: EFD2126 Material: PL7 Bobbin: EFD2126 (c) 2007 Fairchild Semiconductor Corporation FAN7317 * 1.0.2 www.fairchildsemi.com 20 10 1 2 3 4 5 6 7 8 OUTA OLR1 OLR2 OLP2 GND IC1 OUTC CMP ENA CT OLR4 OLP3 OLR3 OLP4 11 ON/OFF BDIM(0~3.3V) FAN7317 -- LCD Backlight Inverter Drive IC 4. Winding Specification Pin No. 5 7 2 9 Wire 1 UEW 0.4 1 UEW 0.04 Turns 17 2256( = 0+0+376*6) Inductance 250H 4.2H Leakage Inductance 16H 290mH Remarks 1kHz, 1V 1kHz, 1V 5. BOM of the Application Circuit Part Ref. F1 R1 R2 R3 R5 R6 R7 R8 R9 R10 R12 R13 R14 R15 R16 C3 C5 C6 C7 C8 C9 C10 C11 C12 Value Fuse 24V 3A Resistor (SMD) 10k 10k 200 100k 10k 200 75k 10k 8.2k 10k 200 1.5M 10k 200 Capacitor (SMD) 1 1 3.3n 10 10n 10 220p 10n 1 Description FUSE 1608 J 1608 J 1608 F 1608 F 1608 J 1608 F 1608 J 1608 J 1608 J 1608 J 1608 F 1608 F 1608 J 1608 F 50V 2012 K 50V 2012 K 50V 1608 K 16V 3216 50V 1608 K 16V 3216 50V 1608 K 50V 1608 K 50V 2012 K Part Ref. C14 C15 C17 C18 C19 C21 C4 C13 C16 C20 C1 C2 M1 M2 CN1 CN2 CN3 CN4 CN5 TX1 TX2 Value 3.3n 100n 1 4.7n 3.3n 3.3n Capacitor (DIP) 3p 3p 3p 3p Description 50V 1608 K 50V 1608 K 50V 2012 K 50V 1608 K 50V 1608 K 50V 1608 K 3KV 3KV 3KV 3KV 25V 25V Fairchild Semiconductor Fairchild Semiconductor Electrolytic capacitor 220 220 MOSFET (SMD) FDD8424H FDD8424H 12505WR-10 35001WR-02A 35001WR-02A 35001WR-02A 35001WR-02A Transformer (DIP) EFD2126 EFD2126 Wafer (SMD) (c) 2007 Fairchild Semiconductor Corporation FAN7317 * 1.0.2 www.fairchildsemi.com 21 FAN7317 -- LCD Backlight Inverter Drive IC Physical Dimensions 13.00 12.60 11.43 20 B 11 A 9.50 10.65 7.60 10.00 7.40 2.25 1 PIN ONE INDICATOR 0.51 0.35 0.25 M 1.27 CBA 10 1.27 0.65 LAND PATTERN RECOMMENDATION 2.65 MAX SEE DETAIL A C 0.33 0.20 0.10 C SEATING PLANE 0.75 0.25 (R0.10) (R0.10) 8 0 X 45 0.30 0.10 NOTES: UNLESS OTHERWISE SPECIFIED GAGE PLANE 0.25 1.27 0.40 (1.40) A) THIS PACKAGE CONFORMS TO JEDEC MS-013, VARIATION AC, ISSUE E B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) CONFORMS TO ASME Y14.5M-1994 E) LANDPATTERN STANDARD: SOIC127P1030X265-20L F) DRAWING FILENAME: MKT-M20BREV3 SEATING PLANE DETAIL A SCALE: 2:1 Figure 58. 20-SOIC Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c) 2007 Fairchild Semiconductor Corporation FAN7317 * 1.0.2 www.fairchildsemi.com 22 FAN7317 -- LCD Backlight Inverter Drive IC (c) 2007 Fairchild Semiconductor Corporation FAN7317 * 1.0.2 www.fairchildsemi.com 23 |
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